High speed, density and reliability requirements for computer system applications of static random access memory (SRAM) require efficient and effective test applications to process and manufacture viable components for high end processor products. Manufacturing yield, and ultimately product cost is an integral part of the ability to design, manufacture, and sell computer systems in the marketplace. A key requirement to achieving leading edge technology implementations is the ability to diagnose problems in the design/manufacturing process for early resolution, in a timely fashion, and to lower overall technology cost, prior to product volume ramp-up. Efficient SRAM/DRAM designs stress the manufacturing process capability due to the high device usage (transistor elements) in a given area (smaller memory cell yields higher number of bits per chip), and the high end processor applications demand high memory bit usage. This yields an increased sensitivity to process defects over the accompanying logic, typically, and this drives the need to analyze, understand, and eventually reduce overall process defect density to achieve product yield and cost requirements.
To this end IBM uses integrated self test, and particularly for the memory arrays, the Array Built In Self Test (ABIST) has been employed to provide deterministic test coverage ensuring high quality products. Diagnosis of fails to initial manufacturing test and subsequent stress screens are critical to yield diagnostics and product reliability improvement efforts, as they are more realistic indicators than monitor structures. Monitor structures are easier to diagnose, but are only models of the product/process interaction, and are expensive from the perspective of area overhead and process productivity.
Diagnosis of array cell failures currently requires execution of the ABIST algorithm, synchronous to an external test system, during which an off-chip fail indicator is monitored, on a cycle-by-cycle basis, to determine at which points in the test the array fails. The external test equipment is used to record the failing cycles, and to repeat the test algorithms stopping “n” cycles prior to each fail, to account for the number of cycles required to “pipe” the fail indicator to an observe point, where the failing state of the array data bus can be scanned off-chip for analysis. Given the failing cycles of the ABIST algorithm, one can calculate the expected memory array data for the test and compare to the failing data scanned from the chip. The combination of the calculation of failing memory array data out, and the algorithmic calculation from the self test engine state to obtain the memory array address location together provide sufficient information for a logical cell determination of the fail. This requires clocking the array in a synchronous manner with the external test exerciser (tester) and the ability to successfully repeat failure on each of multiple passes through the test algorithm.
The technique falls short if the fails are not “hard” repeatable fails. If a fail is on the edge of the point of failure, (“soft” fails) which sometimes fails or not depending on the conditions at the time of execution, it is difficult to capture and verify. Also, AC defects (defects dependent on the speed/rate at which the algorithm is applied) are not detectable if the exerciser (tester) is not able to apply the test algorithm at the failing cycle time. This process is insufficient for diagnosis of those defects that are not detectable at test frequencies that can be provided by external test equipment, but rather rely on on-chip clock frequency multiplication techniques to multiply tester provided clock signal frequencies to those that meet or exceed the intended application.
This process is workable for low incidents of reliability or line return fails, but is insufficient for line monitoring activity or identification of nonrandom manufacturing defects (such as mask defects, also known as “repeaters”) due to the interactive nature of the procedures, and the test hardware and manpower resources required.